Ideally, for power semiconductor devices, such as power transistors, it is desirable that the devices can operate at high voltages which are close to the theoretical breakdown voltage of the semiconductor. However, it is inevitable that during the manufacturing process defects in the semiconductor will be induced which will affect the semiconductor properties (e.g. carrier lifetime, recombination velocity, mobility, etc.) and the resulting device properties. As a result the measured voltage at which breakdown occurs is considerably less than the theoretical breakdown voltage. Thus, the operating voltage of such devices is limited which can be significant for power devices which are required in some applications to operate up to voltages of between 800-900 volts.
Silicon is the most commonly used semiconductor so for convenience of explanation, the description continues using silicon as an exemplary semiconductor material.
A number of methods have been developed in order to increase the measured breakdown voltage capabilities of power devices using planar technology. One of these methods involves processing a device having a guard ring: that is an auxiliary electrode. Such a process is well known in the art. In a NPN transistor, for example, a P+ guard ring is produced during a P+ diffusion step and is positioned so that there is a well defined space between it and the collector electrode of the NPN transistor. The guard ring decreases the electric field at the collector-base junction and thereby increases the voltage capability of the device. However, devices which are produced by this process have maximum operating voltages which are typically about 70% that of the theoretical breakdown voltage.
Another known method which increases the voltage capabilities of power devices by using guard rings requires an additional base drive processing step at a very high temperature, for example over 1200.degree. C. However, this method requires two additional process steps and a temperature domain which introduces crystal defects and a variation in the minority carrier lifetime.
All the methods which use guard rings have a disadvantage in that each guard ring increases the size of the die by as much as 10%-15%. In addition, problems can arise when processing the guard ring since it is extremely important that the space between the collector-base junction and the guard ring is clearly defined in order that the electric field can be sufficiently decreased. A further disadvantage with this method is that the measured voltage at which breakdown occurs is still less than the theoretical breakdown voltage.
A different method which addresses the problem of increasing the voltage capabilities of high voltage power devices requires the use of a field plate. In this case, the devices have a metal plate such as aluminium metal deposited on an isolation oxide. The aluminium plate is etched away so that it extends across only a portion of the isolation oxide near the collector-base junction thereby reducing the junction curvature effect: that is, the curving of the equipotential lines around the collector-base junction. However, at the edge of the aluminium plate the equipotential lines tend to converge and hence the electric field is increased. Silicon oxide is most commonly used because of its excellent compatibility with silicon.
Experiments have shown for such a field plate device that there exists a relationship between the minimum silicon oxide thickness and the resistivity of the semiconductor expitaxial layer in order to obtain the breakdown voltage. Against this, it is also important that the silicon oxide thickness between the collector-base junction and the edge of the aluminium plate is optimised to reduce the electric field at the edge of the aluminium plate. Taking account of these two conflicting requirements the optimum value for such a parameter is known by experiment. However, devices which are produced by this process have maximum operating voltages which are typically only about 60% that of the theoretical breakdown voltage.
A known improvement which utilises a resistive field plate method has been developed. This is similar to the field plate method, however, a semi-insulating polycrystalline semiconductor, such as polycrystalline silicon (SIPOS), is deposited on the silicon oxide which has been exposed by etching away the aluminium plate. Devices produced by such a process can support higher operating voltages, however, such devices suffer from a new problem which is known as the walk out effect.
The walk out effect produces a gradual variation in the measured breakdown voltage which affects the stability of the devices. In order to overcome the effects due to walk out, an additional dielectric layer is deposited using high temperature Chemical Vapour Deposition (CVD) on top of the SIPOS. Typically this second layer may comprise silicon oxide, silicon nitride or phosphosilicate glass. However, although having a CVD second layer reduces the walk out effect, the high resistivity of such a layer compromises the field plate effect and as a result considerably reduces the operating voltage capabilities of the semiconductor power device.